The present invention relates to a stack package, and more particularly, to a semiconductor chip and a stack package having the same that allows chip selection to be easily conducted.
Stack packages in which a plurality of semiconductor chips are stacked to improve data storage capacity has been developed in a variety of shapes. One such stack package comprises, for example, a memory semiconductor chip and a system semiconductor chip stacked to improve data storage capacity and to increase data processing speed.
An example of such a stack package is stack package 100 which uses through-silicon vias (TSVs: hereinafter referred to as ‘through electrodes’) 30 as shown in FIG. 1. The stack package 100 using the through electrodes 30 has a structure in which the through electrodes 30 are formed in respective stacked semiconductor chips 20 such that electrical connections among the semiconductor chips 20 are formed by the through electrodes 30.
In FIG. 1, the unexplained reference numeral 10 designates a substrate, 12 bond fingers, 14 ball lands, 22 bonding pads, 40 an encapsulation member, and 50 solder balls.
In the case of a stack package using through electrodes, chip selection wires are needed for selectively driving the stacked semiconductor chips. In this regard, redistribution lines are conventionally used as chip selection lines. Redistribution lines for through electrodes are currently realized through a vertical passing method as shown in FIG. 2 or a method as shown in FIG. 3 in which additional lines 70 are formed and the additional lines 70 and the bond fingers 12 of the substrate 10 are bonded using conductive wires 80.
In FIGS. 2 and 3, the unexplained reference numerals 24, 32, and 60 designate chip selection pads, additional through electrodes, and redistribution lines, respectively.
However, in the conventional method shown in FIG. 2 for realizing the redistribution lines for through electrodes, a manufacturing procedure is complicated due to forming of the additional through electrodes and the redistribution lines on the respective semiconductor chips. Also, since a predetermined gap is needed between the semiconductor chips, the overall height of the stack package increases. Also, in the conventional method shown in FIG. 3 for realizing the redistribution lines for through electrodes, since additional space for wire bonding is needed, the size of the stack package increases.